1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a test circuit of a multivalued logic circuit.
2. Background of the Invention
In the semiconductor device field, with the large-scaled system and the increasing number of logic gates to be mounted, the number of input/output terminals is also remarkably increased. However, the number of input/output terminals that can be mounted on the semiconductor device is limited by a package. For that reason, there is a case in which a larger package must be employed when the number of input/output terminals exceeds a mountable limit. Under the circumstances, a reduction in the number of input/output is executed by using the multivalued logic circuit. However, there is a need to provide the semiconductor device with a test-use output terminal, which leads to a problem on a reduction in the number of terminals. Further, the number of multivalued logics that can be dealt with in the individual multivalued logic circuits is increased, whereby a technique enabling the multivalued logic circuit to be efficiently tested is increasingly required.
As a test of the semiconductor device including the multivalued logic circuit, there is a threshold voltage test of the multivalued input terminal. JP-A-03-209181 has proposed a method for reducing the number of terminals to be used in a threshold voltage test.
First, a description will be given of the configuration of a semiconductor device discloses in JP-A-03-209181 with reference to FIG. 9. As shown in FIG. 9, an n-valued input terminal 1 is connected with (n−1) comparators C1 to Cn−1. The comparators C1 to Cn−1 are connected to an internal logic 3 and a threshold voltage test circuit 6, respectively. Output terminals 5 are connected to the internal logic 3, respectively, and an output terminal 7 is connected to the internal logic 3 or the threshold voltage test circuit 6 through an output mode selector switch 4. The respective comparators C1 to Cn−1 are set with threshold voltages different gradually such as V1<V2< . . . <Vn−1, respectively.
The operation of testing the semiconductor device shown in FIG. 9 will be described. First, in order to observe an output signal of the threshold voltage test circuit 6 by using the output terminal 7, the output mode selector switch 4 changes over to connect the threshold voltage test circuit 6 and the output terminal 7.
In that state, an input voltage of the n-valued input terminal 1 is sequentially raised from 0 volt, an output signal of the comparator C1 whose threshold voltage is V1 changes to “H” level from “L” level. When the input voltage is raised as it is, an output signal of the comparator C2 whose threshold voltage is V2 changes to “H” level from “L” level. This operation is sequentially repeated with the results that an output signal of the comparator Cn−1 whose threshold voltage is Vn−1 finally changes to “H” level from “L” level.
In this situation, as shown in FIG. 10, a test output signal of the threshold voltage test circuit 6 is also inverted every time the output signals of the comparators C1 to Cn−1 are inverted. That is, an output signal observed at the output terminal is inverted when the input voltage of the n-valued input terminal 1 first reaches V1 volt, and again inverted when the input voltage then reaches V2 volt. This operation is repeated, and when the input voltage of the n-valued input terminal 1 reaches Vn−1 volt, (n−1)-th inversion is conducted.
Accordingly, when the voltage of the n-valued input terminal 1 when the test output signal is inverted is measured, and compared with the threshold voltages of the comparators C1 to Cn−1, it is possible to determine whether the comparators C1 to Cn−1 normally operate, or not.
The above description is applied to a case of typical n-valued input. A specific example of four-valued input will be described. FIG. 11 is a circuit configuration diagram showing the configuration of the threshold voltage test circuit 6 in the case of four-valued input . As shown in FIG. 11, the threshold voltage test circuit 6 includes two inversion logic blocks and three NAND logic blocks. The threshold voltage test circuit 6 is connected to the n-valued input terminal 1 through the comparators C1 to C3, and also to the output terminal 7. With the above configuration, the threshold voltage test circuit 6 sequentially generates inversion logic according to the output signals of the comparators C1 to C3, as shown in a characteristic diagram of FIG. 12.